Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications

By Niccolò Battezzati, Luca Sterpone, Massimo Violante

Embedded platforms purposes which are both project or safety-critical frequently entail low- to mid- construction volumes, require the swift improvement of particular projects, that are mostly computing in depth, and are fee bounded. The adoption of re-configurable FPGAs in such software domain names is restricted to the provision of compatible options to assure the dependability standards entailed by way of severe functions. This publication describes the demanding situations confronted by way of designers while enforcing a venture- or safety-critical software utilizing re-configurable FPGAs and it info a number of recommendations to beat those demanding situations. as well as an summary of the foremost options of re-configurable FPGAs, it presents a theoretical description of the failure modes which may reason unsuitable operation of re-configurable FPGA-based digital structures. It additionally outlines research ideas that may be used to forecast such mess ups and covers the speculation at the back of suggestions to mitigate fault results. This ebook additionally experiences present applied sciences to be had for development re-configurable FPGAs, in particular SRAM-based expertise and Flash-based expertise. for every expertise brought, theoretical innovations offered are utilized to genuine situations. layout concepts and instruments are offered to improve serious functions utilizing advertisement, off-the-shelf units, resembling Xilinx Virtex FPGAs, and Actel ProASIC FPGAs. substitute options in keeping with radiation hardened FPGAs, comparable to Xilinx SIRF and Atmel ATF280 also are provided. This publication is a useful reference for an individual attracted to knowing the applied sciences of re-configurable FPGAs, in addition to designers constructing serious purposes in accordance with those applied sciences.

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All of the circuits were synthesized with the Xilinx ISE circulation after which hardened with the Xilinx TMR instrument and the FT-TDP set of rules. the entire circuits were synthesized utilizing the Xilinx TMR software and so they were applied utilizing diverse SRAM-based FPGAs of the Virtex-II relations synthetic by way of Xilinx [10]. The circuit’s features are said in desk 6. 2 the place we indicated the variety of flip-flops (FFs), look-up tables (LUTs), similar gates, the world N. Battezzati et al. , Reconfigurable box Programmable Gate Arrays for Mission-Critical purposes, DOI 10. 1007/978-1-4419-7595-9_6, C Springer Science+Business Media, LLC 2011 187 188 6 placing Mitigation options at paintings Circuits desk 6. 1 Benchmark TMR software circuit’s implementation features Description machine FFs (#) LUTs (#) an identical gates (#) B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 Serial stream comparator FSM for BCD numbers source arbitrer Compute min and max complicated reminiscence content material Interrupt handler count number issues on-line locate series inclusions Serial to serial converter vote casting process Scramble string cipher bet series Interface to meteo sensor Viper processor XC2V40 XC2V40 XC2V40 XC2V40 XC2V80 XC2V40 XC2V40 XC2V40 XC2V40 XC2V40 XC2V40 XC2V250 XC2V40 XC2V1500 three three 33 sixty seven forty five four fifty one nine 28 18 38 141 36 188 nine four seventy five 151 265 nine a hundred and forty forty fifty three fifty two a hundred thirty five 361 sixty three 2, 388 106 fifty nine 749 1, 625 2, 172 121 1, 347 411 545 507 1, 192 three, 428 763 19, 660 Circuits desk 6. 2 Benchmark TMR device circuit’s implementation features FFs [#] LUTs [#] similar gates [#] region TMR [#] Voter congestion [%] B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 15 12 111 201 a hundred thirty five 24 153 39 eighty four sixty six 114 423 114 666 33 15 237 501 903 forty five 468 132 one hundred sixty five a hundred and eighty 441 1, 119 228 7, 782 372 192 2, 355 five, 235 7, 488 525 four, 401 1, 341 1, 680 1, 719 three, 846 10, 554 2, 613 sixty three, 174 three. fifty one three. forty six three. 14 three. 22 three. forty five four. 34 three. 27 three. 26 three. 08 three. 39 three. 23 three. 08 three. forty two three. 21 21. 05 15. forty five thirteen. seventy seven 35. fifty one thirteen. 10 12. 31 2. sixty nine 14. 10 1. sixty two 15. 00 eight. ninety one forty five. eighty two 17. ninety nine forty seven. eighty three overhead with admire to the unique circuits according to the variety of similar gates and the routing congestion a result of voter assets. The TMR circuits are greater greater than thrice the unique ones because the TMR implementation calls for additional extra common sense so as to enforce the voter common sense and routing constitution. because the reader can detect, the routing voter congestion depends at the complexity of every circuit. particularly, it really is concerning the variety of used flip-flops, considering each one flip-flop is possibly secure by means of a voter constitution. The voter constructions were immediately inserted into the circuit common sense via the Xilinx TMR device. so as to estimate the delicate configuration reminiscence bits, we use the static analyzer instrument offered in [8] which can establish the configuration reminiscence bit that if plagued by an SEU may possibly impress an mistakes at the output of the circuit. We run the static analyzer instrument at the unique unhardened circuits, the X-TMR circuits, 6.

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